1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method of the same.
2. Related Background Art
In a semiconductor device including two or more kinds of convex protrusions, it is sometimes wished to leave a sidewall material to form a sidewall only on a side surface of a part of the protrusions. An FinFET in FIG. 1 shows an example of a semiconductor device in which whether to form a sidewall or not depends on each protrusion.
In the semiconductor device shown in FIG. 1, provided on a buried insulating film 8 formed from a BOX (Buried Oxide) are a gate electrode 10 as a second protrusion and a Fin 12 as a first protrusion which becomes a source/drain. On the upper side of the gate electrode 10, a SiN hard mask 11 is provided, and on the upper side of the Fin 12, a SiN hard mask 13 is provided.
However, when a side wall is formed in a sidewall-leaving process, there is a problem that sidewalls are formed on all of the protrusions. Namely, in the semiconductor device shown in FIG. 1, as shown in FIG. 2, it is necessary to form a sidewall 14 on a sidewall portion of the gate electrode 10. However, when the sidewall 14 is formed in the gate electrode 10, a sidewall 16 is inevitably formed also in the Fin 12.
If the sidewall 16 is formed in the Fin 12, when ion implantation into the Fin 12 is performed to form source/drain regions in the Fin 12, ion implantation from the sidewall of the Fin 12 cannot be performed. Hence, ion implantation is performed from above the Fin 12.
FIG. 3 is a sectional view taken along the line A-A′ in FIG. 2. As shown in FIG. 3, if ion implantation into the Fin 12 is performed from above, source/drain regions 18 which are uniform in a depth direction of the Fin 12 cannot be formed. If the source/drain regions 18 uniform in the depth direction cannot be formed, a distance L1 between the source region and the drain region in an upper portion of the Fin 12 and a distance L2 between the source region and the drain region in a lower portion of the Fin 12 become different. Moreover, a high parasitic resistance R occurs in the source/drain regions 18 in the lower portion of the Fin 12. Therefore, there arises a problem that transistor drive capability deteriorates.
However, when the sidewall 14 is not formed, if thermal diffusion is performed after ion implantation is performed to form the source/drain regions 18 in the Fin 12, there arises a problem that the source/drain regions 18 are united to each other. Moreover, if the sidewall 14 is not formed, there is another problem that when silicide 19 is formed in the upper portions of the source/drain regions 18, the silicide 19 formed in the source/drain regions 18 and silicide formed in the gate electrode 10 are united.
Furthermore, the technology of forming a pattern which is finer than the limit of photolithography by using the sidewall formed in the sidewall-leaving process as an etching pattern is known. Such a process is called a sidewall pattern transfer process, and, for example, disclosed in Yang-Kyu Choi, Tsu-Jae King, Chenming Hu, “A Spacer Patterning Technology for Nanoscale CMOS”, IEEE Transactions on Electron Devices, Vol. 49, No. 3, March 2002, pp. 436-441 (Document 1).